The present invention relates to a method of fabricating a semiconductor device, and particularly to planarization of a polysilicon film which is one constituent film of a semiconductor device, and which for example is deposited to fill a trench such as a hole or groove provided in a silicon substrate. The invention provides a particular advantage where the trench is a deep trench having an aspect ratio (depth/width) of more than 1 (unity).
Prior-art examples of technology for depositing polysilicon to fill a trench such as a hole or groove formed in a silicon substrate for the purpose of planarization are disclosed in Japanese Patent Application Laid-open No. 226141/1985, Japanese Patent Application Laid-open No. 170951/1985, and Japanese Patent Application Laid-open No. 226128/1985.
With increasing demand for higher integration of a semiconductor devices, such as dynamic random access memory (DRAM) the trench capacitor configuration is often adopted. In trench capacitor configuration, a trench such as a hole (a trench with a limited length) or groove (a trench with a considerable length, such as a one surrounding a memory cell) is formed in a silicon substrate and the surface perpendicular to the principal plane of the substrate is utilized for the formation of the electrode.
The details of the process of formation of the trench capacitor differ from one cell configuration to the another. But it generally comprises a step of forming a trench such as a hole or groove in a silicon substrate, a step for depositing a gate electrode, and a step of subsequently planarizing the surface of the substrate.
FIG. 1A to FIG. 1C show an example of planarization process. For simplicity of illustration, the gate electrode is omitted. First, as illustrated in FIG. 1A, a stopper oxide film 2 is formed in a deep trench 1a with a width W0 of the opening formed in a silicon substrate 1.
Next, as shown in FIG. 1B, filling polysilicon 3 is formed by CVD (chemical vapor deposition) to a thickness of not smaller than 1/2 of the width W1 of the opening. Thereafter, reactive ion etching (RIE) is performed to etch and remove the polysilicon 3 until the stopper oxide film 2 is exposed, as shown in FIG. 1C.
A problem associated with the above-described method is that a small dent 5 is formed in the center of the area in which the trench has been filled with polysilicon 3. Moreover, the central region 4 of the area in which the trench has been filled with the polysilicon 3 is formed of a joint of the films that have grown from opposite sides so that the etching rate of this region is high. As a result, a step 6, as shown in FIG. 1C, is formed.
The dimension of the step 6 has a correlation with the film thickness of the polysilicon 3. With the smaller film thickness of the polysilicon 3, the dimension of the step 6 is increased.
To reduce the dimension of the step 6, precise control on the termination of etching of the polysilicon 3 is required. This is because when the stopper oxide film 2 is exposed, the surface of the polysilicon is reduced and the etching rate of the polysilicon 3 is rapidly increased. This means that fluctuation of the detection of the termination leads to fluctuation of dimension of the step 6.
The step will result in a step in the underlying layer during the subsequent conductor layer formation and can cause disconnection or etching residue.
A measure to prevent the step formation is to apply organic or inorganic planarizing material onto the polysilicon and then uniformly etch from the planarized surface.
However, resist, polyimide or coating-type SiO.sub.2 film, known as organic or inorganic planarizing material had to be applied to a great thickness to be sufficiently plane.
When the thick planarizing material is used, the time required for uniformly etching the planarizing material and the polysilicon 3 is long.
Moreover, it was very difficult to control the etching rates of the underlying polysilicon and the planarizing material to be equal, and perform uniform etch-back.